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US3022
4 BIT PROGRAMMABLE SYNCHRONOUS BUCK PLUS FOUR LDO CONTROLLER
PRELIMINARY DATASHEET
FEATURES
Provides Single Chip Solution for Vcore, GTL+ ,AGP Bus, 1.8V , 2.5V Automatic Voltage Selection for AGP slot's Vddq supply 4 Linear regulator controller on board to achieve lowest system cost solution Standby Vref provides reference for the ACPI regulators Designed to meet Intel Latest VRM specification for next generation micrprocessors On board DAC programs the output voltage from 1.3V to 2.05V On board resistor dividers provides lowest component count Loss less Short Circuit Protection for all outputs Synchronous operation allows maximum efficiency Patented architecture allows fixed frequency operation as well as 100% duty cycle during dynamic load Soft Start High current totem pole driver for direct driving of the external Power MOSFET Power Good function Monitors all Outputs OVP Circuitry Protects the Switcher Output and generates a Fault output
DESCRIPTION
The US3022 is the first controller IC with five controller in one package specifically designed to meet Intel specification for next generation microprocessor applications requiring multiple on board regulators . The US3022 provides a single chip controller IC for the Vcore , 4 LDO controllers, one with the automatic select pin that connects to the TYPE DETECT pin of the AGP slot for the AGP Vddq supply, one for GTL+ , the other for the 1.8V chip set regulator as well as 2.5V for the clock as required for the next generation PC applications. The US3022 typically uses Bipolar transistors for Vout3(1.5V) and Vout4(1.8V) and Vout5 however if Vaux pin is connected to 12V, then MOSFETs can also be used as external pass elements. No external resistor divider is necessary for any of the regulators. The switching regulator feature a patented topology that in combination with a few external components as shown in the typical application circuit ,will provide well in excess of 20A of output current for an on- board DC/DC converter while automatically providing the right output voltage via the 5 bit internal DAC .The US3022 also features, loss less current sensing for both switcher by using the Rds-on of the high side Power MOSFET as the sensing resistor, an output under voltage shutdown that detects short circuit condition for the linear outputs and latches the system off, and a Power Good window comparator that switches its open collector output low when any one of the outputs is outside of a pre programmed window.
APPLICATIONS
Total Power Soloution for Next Generation Intel Processor application
TYPICAL APPLICATION
5V 3.3V LINEAR CONTROL SWITCHER CONTROL Vout1
Vout2
US3022
LINEAR CONTROL Vout3
LINEAR CONTROL
LINEAR CONTROL Vout4
3022app3-1.0
Vout5
PACKAGE ORDER INFORMATION
Ta (C) 0 TO 70
Rev. 1.0 11/2/99
Device US3022CW
Package 28 pin Plastic SOIC WB
4-1
US3022
ABSOLUTE MAXIMUM RATINGS
V5 supply Voltage ........................................... 7V V12 Supply Voltage ............................................ 20V Storage Temperature Range ................................. -65 TO 150C Operating Junction Temperature Range .......... 0 TO 125C
PACKAGE INFORMATION
28 PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
Drive2 1 Vsen5 2 Vref 3 VID3 4 VID2 5 VID1 6 VID0 7 PGood 8 Vsen2 9 Drive5 10 Select 11 SS 12 Fault / Rt 13 Vsen4 14
28 V12 27 UGate 26 Phase 25 LGate 24 PGnd 23 OCSet 22 Vsen1 21 Fb 20 V5 19 Vsen3 18 Drive3 17 Gnd 16 Vaux 15 Drive4
JA =80C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified ,these specifications apply over ,V12 = 12V, V5 = 5V and Ta=0 to 70C. Typical values refer to Ta =25C. Low duty cycle pulse testing are used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS Supply UVLO Section UVLO Threshold-12V Supply ramping up 10 V UVLO Hysterises-12V 0.6 V UVLO Threshold-5V Supply ramping up 4.4 V UVLO Hysterises-5V 0.3 V Supply Current Operating Supply Current V12 6 mA V5 30 Switching Controllers; Vcore (Vsen 1) and AGP (Vsen 2) VID Section (Vcore only) DAC output voltage (note 1) 0.99Vs Vs 1.01Vs V DAC Output Line Regulation 0.1 % DAC Output Temp Variation 0.5 % VID Input LO 0.8 V VID Input HI 2 V VID input internal pull-up resistor to V5 27 k Vsen2 Voltage Select<0.8V 1.5 V Select>2V 3.3 V
4-2
Rev. 1.0 11/2/99
US3022
Error Comparator Section Input bias current Input Offset Voltage Delay to Output Current Limit Section C.S Threshold Set Current C.S Comp Offset Voltage Hiccup Duty Cycle Output Drivers Section Rise Time Fall Time Dead band Time Between High side and Synch Drive (Vcore Switcher Only) Oscillator Section (internal) Osc Frequency 1.8V Regulator (Vsen 4) Vsense Voltage Vo4 Vsense Voltage Input bias current Output Drive Current 1.5V Regulator (Vsen 3) Vsense Voltage Vsense Voltage Input bias current Output Drive Current 2.5V Regulator (Vsen 5) Vsense Voltage Vsense Voltage Input bias current Output Drive Current Power Good Section Vsen1 UV lower trip point Vsen1 UV upper trip point Vsen1 UV Hysterises Vsen1 HV upper trip point Vsen1 HV lower trip point Vsen1 HV Hysterises Vsen2 trip point Vsen4 trip point Vsen3 trip point Vsen5 trip point Power Good Output LO Power Good Output HI Fault (Overvoltage) Section Core O.V. upper trip point Core O.V. lower trip point FAULT Output HI Soft Start Section Soft Start Current -2 Vdiff=10mV 200 -5 Css=0.1 uF CL=3000pF CL=3000pF 10 70 70 +5 2 +2 100 uA mV nS uA mV % nS nS
CL=3000pF Rt=Open Ta=25, Drive4 = Vsen4
200 217 1.800 1.800 2 50
nS Khz V V uA mA
Vaux-Vdrive>0.6V
Vo3
Ta=25, Drive3 = Vsen3
1.500 1.500 2 50 2.500 2.500 2 50 0.90Vs 0.92Vs .02Vs 1.10Vs 1.08Vs .02Vs 1.100 2.560 1.320 1.140 1.875 0.4 4.8 1.17Vs 1.15Vs 10 20
Vaux-Vdrive>0.6V Vo5 Ta=25, Drive5 = Vsen5
V V uA mA V V uA mA V V V V V V V V V V V V V V V V uA
Vaux-Vdrive>0.6V Vsen1 ramping down Vsen1 ramping up Vsen1 ramping up Vsen1 ramping down Select<0.8V Select>2V
RL=3mA RL=5K pull up to 5V Vsen1 ramping up Vsen1 ramping down Io=3mA OCset=0V , Phase=5V
Note 1: Vs refers to the set point voltage given in Table 1.
Rev. 1.0 11/2/99
4-3
US3022
Vref Section Vref Initial Accuracy Vref Initial Accuracy Vref Change with Load Vref Output Impedance VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 No Load,Ta=25 No Load, Over Temp No Load to 30K load 1.980 1.960 -2 150 2.000 2.000 300 2.020 2.040 600 V V % Ohm
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Vs 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05
Table 1 - Set point voltage vs. VID codes
PIN DESCRIPTIONS
PIN# PIN SYMBOL 7 VID0 Pin Description LSB input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic "1" as either HI or Open. When left open,his pin is pulled up internally by a 27k resistor to 5V supply. Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic "1" as either HI or Open. When left open,his pin is pulled up internally by a 27k resistor to 5V supply. Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic "1" as either HI or Open. When left open,his pin is pulled up internally by a 27k resistor to 5V supply. MSB input to the DAC that programs the output voltage. This pin is TTL compatible that realizes a logic "1" as either HI or Open. When left open,his pin is pulled up internally by a 27k resistor to 5V supply. This pin provides a 2V reference that remains on when the 5V pin is connected to the 5V standby of the ATX supply. In this application, the Vref pin is used to provide reference for the ACPI regulators. This pin is an open collector output that switches LO when any of the outputs are outside of the specified under voltage trip point. It also switches low when Vsen1 pin is more than 10% above the DAC voltage setting. This pin provides the feedback for the synchronous switching regulator. Typically this pin can be connected directly to the output of the switching regulator. However, a resistor divider is recommended to be connected from this pin to vout1 and GND to adjust the output voltage for any drop in the output voltage that is caused by the trace resistance. The value of the resistor connected from Vout1 to FB1 must be less than 1000. This pin controls the gate of an external MOSFET for the AGP linear regulator. This pin controls the gate of an external transistor for the 2.5V Clock linear regulator.
Rev. 1.0 11/2/99
6
VID1
5
VID2
4
VID3
3
Vref
8
PGOOD
21
FB
1 10
Drive2 Drive5
4-4
US3022
PIN# PIN SYMBOL 22 Vsen1 9 Vsen2 Pin Description This pin is internally connected to the undervoltage and overvoltage comparators sensing the Vcore status. It must be connected directly to the Vcore supply. This pin provides the feedback for the AGP linear regulator. The Select pin when connected to the "Type Detect" pin of the AGP slot automatically selects the right voltage for the AGP Vddq. This pin controls the gate of an external MOSFET for the 1.8V chip set linear regulator. This pin is connected to the Drain of the power MOSFET of the Core supply and it provides the positive sensing for the internal current sensing circuitry. An external resistor programs the C.S threshold depending on the Rds of the power MOSFET. An external capacitor is placed in parallel with the programming resistor to provide high frequency noise filtering. This pin is connected to the Source of the power MOSFET for the Core supply and it provides the negative sensing for the internal current sensing circuitry. This pin provides the soft start for all the regulators. An internal current source charges an external capacitor that is connected from this pin to GND which ramps up the outputs of the regulators, preventing the outputs from overshooting as well as limiting the input current. The second function of the Soft Start cap is to provide long off time (HICCUP) for the synchronous MOSFET during current limiting. This pin has dual function. It acts as an output of the OVP circuitry or it can be used to program the frequency using an external resistor . When used as a fault detector, if any of the switcher outputs exceed the OVP trip point, the FAULT pin switches to 12V and the soft start cap is discharged. If the FAULT pin is to be connected to any external circuitry, it needs to be buffered. This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator. This pin provides the feedback for the linear regulator that its output drive is Drive3. This pin is normally connected to 3.3V or 5V input. When connected to the 12V supply, it provides gate drive voltage for the # 3, #4 and #5 (Drive 3,4,5) linear regulator's pass transistors in case MOSFET transistors are being used instead of Bipolars. This pin provides the feedback for the linear regulator that its output drive is Drive4. This pin serves as the ground pin and must be connected directly to the ground plane. This pin serves as the Power ground pin and must be connected directly to the GND plane close to the source of the synchronous MOSFET. A high frequency capacitor (typically 1 uF) must be connected from V12 pin to this pin for noise free operation. Output driver for the synchronous power MOSFET for the Core supply. Output driver for the high side power MOSFET for the Core supply. This pin is connected to the 12 V supply and serves as the power Vcc pin for the output drivers. A high frequency capacitor (typically 1 uF) must be placed close to this pin and PGND pin and be connected directly from this pin to the GND plane for the noise free operation. 5V supply voltage. A high frequency capacitor (0.1 to 1 uF) must be placed close to this pin and connected from this pin to the GND plane for noise free operation. This pin provides automatic voltage selection for the AGP switching regulator. When it is pulled LO, the voltage is 1.5V and when left open or pulled to HI, the voltage is 3.3V. This pin provides the feedback for the linear regulator that its output drive is Drive5.
15 23
Drive4 OCSET
26 12
PHASE SS
13
FAULT/Rt
18 19 16
Drive3 Vsen3 Vaux
14 17 24
Vsen4 GND PGND
25 27 28
LGATE UGATE V12
20 11 2
V5 Select Vsen5
Rev. 1.0 11/2/99
4-5
US3022
BLOCK DIAGRAM
V12 V5
Enable
Fb
1.17Vset Over Voltage Vset Enable V12
UVLO
UGate PWM Control
V12
Vsen1 PGood Vsen3 Vsen4
+
1.1Vset
Slope Comp
LGate Osc Phase
Over Current
0.9Vset
Enable
Vaux Drive4
R 1.26V 3R
Soft Start & Fault Logic
OCSet 200uA PGnd Gnd Fault / Rt SS
Vset
Drive3 Select
R 3R 1.5V 3.3V
VID0 VID1 4Bit DAC VID2 VID3
Drive2 Vsen2
R 3R 2.5V
+
Vref
2V
Drive5 Vsen5
3022blk1-1.0
Figure 1 - Simplified block diagram of the US3022.
4-6
Rev. 1.0 11/2/99
US3022
TYPICAL APPLICATION
+5Vin
L1
12V + R1 2.21K C5 1UF 28 16 3.3Vin + C6 220UF Q2 IRL3103S 1 25 5.1 24 9 Vout2(1.5V or 3.3V) + C13 680uf 21 20 C14 11 TYPE DETECT# Q4 MJD200 18 19 Vout3 (1.5V) + C15 680uf Q5 MJD200 7 15 6 VID2 14 Vout4(1.8V) + C16 680uf Q6 PMBT2222A 4 10 3 2 17 Vout5(2.5V) + C17 220uf 0.1uF C18 12 13 Fault/Rt C19 0.1uF Vref(2V) 5 VID3 VID1 VID0 8 1UF 22 26 R3 Q3 IRL3103S 23 27 5.1 C4 220PF R2 Q1 IRL3103S L2 2.5UH 1500uf C2 + C3
1UH
+
C1 680uf
1500uf 6MV1500DX
VCORE
+
C7 1500uf
+
C8 1500uf
+
C9 1500uf
+
C10 1500uf
+
C11 1500uf
+
C12 1500uf 6MV1500DX
US3022
5VSB
PGood
The Vref(2V) can be used to provide reference for the ACPI regulatos. In this application the ACPI regulators are designed using op-amp and discrete transistors.
Figure 2 - Typical application of US3022 for an on board DC-DC converter providing power for the Vcore , GTL+, 1.8V chip set supply, 2.5V clock supply as well as auto select AGP supply for the next generation PC applications.
Rev. 1.0 11/2/99
4-7

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